详细讲解6状态机建模ppt课件.pptVIP

VHDL教程;为什么要使用状态机;数据类型定义语句;状态机的每一状态在实际电路中是以一组触发器的当前二进制数位的组合来表示的，但设计者在状态机的设计中，为了便于阅读、编译和优化，往往将表征每一状态的二进制数组用文字符号来代表，即所谓状态符号化。例如： TYPE m_state IS（st0,st1,st2,st3,st4,）； SIGNAL present_state, next_state : m_state;;;6.1 有限状态机的一般结构;2.主控时序进程 负责状态机运转和在时钟驱动下负责状态机转化的进程。状态机是随外部信号、以同步时序方式工作的。因此，状态机必须包含一个对工作时钟信号敏感的进程，作为状态机的“驱动泵”。;4.辅助进程 用于配合状态机工作的组合进程或时序进程。;【例6-1】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS PORT ( clk,reset : IN STD_LOGIC; state_inputs : IN STD_LOGIC_VECTOR (0 TO 1); comb_outputs : OUT INTEGER RANGE 0 TO 15 ); END s_machine; ARCHITECTURE behv OF s_machine IS TYPE FSM_ST IS (s0, s1, s2, s3); SIGNAL current_state, next_state: FSM_ST; BEGIN REG: PROCESS (reset,clk) BEGIN IF reset = 1 THEN current_state = s0; ELSIF clk=1 AND clkEVENT THEN current_state = next_state; END IF; END PROCESS; ;COM:PROCESS(current_state, state_Inputs) BEGIN CASE current_state IS WHEN s0 = comb_outputs= 5; IF state_inputs = 00 THEN next_state=s0; ELSE next_state=s1; END IF; WHEN s1 = comb_outputs= 8; IF state_inputs = 00 THEN next_state=s1; ELSE next_state=s2; END IF; WHEN s2 = comb_outputs= 12; IF state_inputs = 11 THEN next_state = s0; ELSE next_state = s3; END IF; WHEN s3 = comb_outputs = 14; IF state_inputs = 11 THEN next_state = s3; ELSE next_state = s0; END IF; END case; END PROCESS; END behv;;6.2 状态机建模;library IEEE,BOOK_LIB; use IEEE.std_LOGIC_1164.all; use BOOK_LIB.UTILS_PKG.all; entity MULTIPLY is port(MPLR,MCND:in STD_LOGIC_VECTOR(15 downto 0); --MPLR是乘数，MCAND是被乘数。 CLOCK,RESET:in STD_LOGIC; DONE:out STD_LOGIC; ACC:buffer STD_LOGIC_VECTOR(31 downto 0)); end; architecture STATE_MACHINE of MULTIPLY is tupe STATE_TYPE