中科院研究生院课程VLSI测试及可测试性设计.pptVIP

EE141 EE141 Chapter 5 What is this chapter about? Basic concepts of logic BIST BIST Design Rules Test pattern generation techniques Output response analysis techniques Logic BIST Architecture Fault Coverage Enhancement Various BIST timing control diagrams A Design Practice Introduction What are the problems in today’s semiconductor testing? Traditional test techniques become quite expensive No longer provide sufficiently high fault coverage Why do we need built-in self-test (BIST)? For mission-critical applications Detect un-modeled faults Provide remote diagnosis BIST Techniques Categories Online BIST Concurrent online BIST Non Concurrent online BIST Offline BIST Functional offline BIST Structural offline BIST A General Form of Logic BIST A Typical Logic BIST System BIST Design Rules Typical X-bounding Methods X-bounding Methods Typical Unknown Sources Analog Blocks Adding bypass logic. Adding control-only scan point Memories and Non-Scan Storage Elements Bypass logic Initialization Combinational Feedback Loops Scan points Typical Unknown Sources (cont’d) Asynchronous Set/Reset Signals using the existing scan enable (SE) signal to protect each shift operation and adding a set/reset clock point (SRCK) on each set/reset signal to test the set/reset circuitry. Typical Unknown Sources (cont’d) Asynchronous Set/Reset Signals Typical Unknown Sources (cont’d) Tri-State Buses Re-synthesize each bus with multiplexers. One-hot decoder Typical Unknown Sources (cont’d) False Paths 0-control point 1-control point Critical Paths Adding an extra input pin to a selected combinational gate on the critical path. Typical Unknown Sources (cont’d) Multiple-Cycle Paths 0-control point 1-control point Holding certain scan cell output states Floating Ports PI or PO must have a proper connection to Power (Vcc) or Ground (Vss). Floating inputs to any internal modules must be avoided. Typical Unknown Sources (cont’d) Bi-directional I/O Ports Fix the direction of e