fpga的安置优化方法综述--外文翻译.docxVIP

附录A FPGA Placement Optimization Methodology Survey Sang-Joon Lee and Dr. Kaamran Raahemifar Department of Electrical and Computer Toronto ABSTRACT Field Programmable Gate Array (FPGA) is a programmable chip that can be used to quickly implement any digital circuits. Placement is an important part of FPGA design step which determines physical arrangement of the logic blocks in the FPGA. The quality of placement of logic blocks determines overall performance of the logic implemented in the FPGA. In this paper, a number of placement optimization techniques are reviewed; min-cut, quadratic, simulated annealing, and a hybrid approach of using genetic algorithm with simulated annealing technique. The methodology of each optimization technique is presented and its advantages and disadvantages are evaluated. Overall, the hybrid approach of using genetic algorithm with simulated annealing technique produces best result, reaching a global optimal solution. The hybrid approach of using genetic algorithm and simulated annealing optimization technique is implemented using MATLAB and its results are presented using a wire-lengthdriven placement as cost function. Index Terms Field programmable gate arrays, optimization methods, routing, quadratic programming, simulated annealing, and genetic algorithms 1. INTRODUCTION Field-Programmable gate arrays (FPGA) are reprogrammable logic chips that can be configured to implement various digital circuits. The Field Programmable Gate Array (FPGA) has gained its popularity in implementing digital circuit due to its significant low cost and fast prototyping turn around time. In this survey, an island style FPGA model is considered. Island style FPGA architecture is generally characterized by its two-dimensional symmetry. The generic structure consists of four main elements: Configurable Logic Blocks (CLB), which typically contains either combinational or sequential logic circuits, Input/Output blocks (IOB), which connects the FPGA