姜书艳 数字逻辑设计及应用 17知识课件.pptVIP

Chapter 7 Sequential Logic Design Principles( 时序逻辑设计原理 );Basic Concepts (基本概念);Basic Concepts (基本概念);Basic Concepts (基本概念);Basic Concepts (基本概念);Basic Concepts (基本概念);思考：能否只用一片1位 全加器进行串行加法？？;暂存;7.1 Bistable Elements (双稳态元件);7.1 Bistable Elements (双稳态元件);Vin1;Metastable Behavior(亚稳态特性);所有的时序电路对亚稳态都是敏感的;7.2 Latches and Flip-Flops(锁存器与触发器);7.2 Latches and Flip-Flops(锁存器与触发器);S-R Latch (S-R锁存器) S-R Latch with Enable (具有使能端的S-R锁存器) D Latch (D锁存器) Edge-Triggered D Flip-Flops (边沿触发式D触发器) Edge-Triggered D Flip-Flops with Enable (具有使能端的边沿触发式D触发器);Scan Flip-Flops (扫描触发器) Master/Sla