低功耗集成锁相环路设计方法-电路与系统专业论文.docx

Low-Power Integrated PLL Design Method ABSTRACT With the high-speed development of microelectronic and integrated circuit technology, power dissipation becomes the most important consideration in ASIC design, except speed and area, so tremendous business occasions lie in low-power design. The intrinsical physical characteristics of the power dissipation determine the close relationship of circuit design and physical design in the low-power circuits design. In the front-end circuit design, how to understand the effect of circuit design impacting upon the physical design is the key of a good circuit design. Low-power design will be more and more focused on with the development of the deep sub-microelectronic technology. Because of the requirement of low-power PLLs in reality, on the base of BL1.2ì m CMOS process, this thesis analyzes how to design a low-power analog-digital mixed PLL. With good performance, we use several low-power design technologies, such as falling the power supply, improving circuit structures and using several power supplies, in order to reduce the power dissipation of the whole system. The reasons of PFD dead zone are analyzed and take the way of extending the high level pulse width to minimize it. In order to advance the stability of the charge-pump, a novel circuit structure is used, eliminating the discontinuity of power supply. Finally, the simulation results of HSpice show that with 3.3V analog power supply and 2V digital power supply, the power dissipation of the whole system is 8.2mw, reducing 54.4% with fairly performance comparing to the one under 5V power supply. Key Words: PLL, Low-Power Design, PFD, Charge-Pump, VCO 上海交通大学硕士学位论文参考文献 上海交通大学硕士学位论文 参考文献 [1】R E Best，Phase-Locked Loops，Theory,Design and Applications，McGraw—Hill， 2“。ed．1993 ISBN 0-07—911386．9 [2is Haykin，An Introduction to Analog and Digital Communications，John Wiley and Sons，1989 ISBN 0-7803—1149—3 [3137福昌，鲁昆生，锁相技术，华中理工大学出版社，1992 [4]胡华春，石玉，数字锁相环路原理与应用，上海科学技术出版社，1 990 [5