Vhdl102可调数字钟.docVIP

--LCD1602数字钟-- Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity clock is Port( rst,clk : in std_logic; rs,en,rst_out,sec_out: out std_logic; rw : out std_logic; data_out : out std_logic_vector(7 downto 0); RD,WR : IN STD_LOGIC; --读写控制 DATA_O ,CONT_O : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --数据输出 DATA_I,CONT_I : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --数据和地址输入 SCLK : OUT STD_LOGIC; IO : INOUT STD_LOGIC; IOB : OUT STD_LOGIC ; k1,k2 : IN STD_LOGIC); End clock; Architecture fwm of clock is TYPE states IS(hold,func_set,dis_on,mode_set,write_char1,write_char2,write_char3,write_char4,write_char5,write_char6, write_char7,write_char8,write_char9,write_char10,return_home,toggle_e,rst1,rst2,rst3,dis_off,dis_clr); SIGNAL state,n_state:states; SIGNAL s0,s1,m0,m1,h0,h1,t: std_logic_vector(3 downto 0); SIGNAL clk_400Hz,clk_10Hz,clk_40Hz: std_logic; SIGNAL DATA_TEMP : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CONT_TEMP : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL SECOND : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL MINUTE : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL HOUR : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL DAY : STD_LOGIC_VECTOR(7 DOWNTO 0); CONSTANT PROCECT : STD_LOGIC_VECTOR: --保护位 CONSTANT SECOND_WRITE: STD_LOGIC_VECTOR: CONSTANT SECOND_READ : STD_LOGIC_VECTOR: CONSTANT MINUTE_WRITE: STD_LOGIC_VECTOR: CONSTANT MINUTE_READ : STD_LOGIC_VECTOR: CONSTANT HOUR_WRITE : STD_LOGIC_VECTOR: CONSTANT HOUR_READ : STD_LOGIC_VECTOR: CONSTANT DAY_WRITE : STD_LOGIC_VECTOR: CONSTANT DAY_READ : STD_LOGIC_VECTOR: -- CONSTANT MONTH_WRITE : STD_LOGIC_VECTOR: -- CONSTANT MONTH_READ : STD_LOGIC_VECTOR: -- CONSTANT YEAR_WRITE : STD_LOGIC_VECTOR: -- CONSTANT YEAR_READ