[工学]t分estbench设计初步.pptVIP

Testbench实例 六进制计数器的验证 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt6_tb is end cnt6_tb; architecture rtl of cnt6_tb is component cnt6 port( clr,en,clk :in std_logic; q :out std_logic_vector(2 downto 0)); end component; signal clr :std_logic:=0; signal en :std_logic:=0; signal clk :std_logic:=0; signal q :std_logic_vector(2 downto 0); constant clk_period :time :=10 ns; begin DUT:cnt6 port map(clk=clk,en=en,clr=clr,q=q); Testbench实例 六进制计数器的验证（续） clk_gen:process begin