支持IEEE1149.7的调试与测试系统关键技术分析.pdfVIP

Abstract Abstract Following the fast development of electron information technology, multi IP core is integrated in one chip to fulfill various new functions, but single chip multi core design at the same time integrates test access port controller of each core (TAPC). Boundary scan testing technology based on IEEE 1149.1 standard (JTAG) can not meet the debug and test requirement of chip design. IEEE 1149.7 standard (CJTAG) is r