段辉高10现代CMOS工艺基本流程汇总.pptVIP

* Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 IMD淀积 金属间绝缘体(IMD)淀积 未掺杂的SiO2 连续的CVD和刻蚀工艺，厚度约1um 填充在金属线之间，提供金属层之间的绝缘隔离 * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 IMD抛光 IMD抛光 CMP * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 Photoresist 光刻胶成形 光刻胶成形 用于定义通孔(Vias) * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 Photoresist IMD1 通孔刻蚀 通孔刻蚀 基于氟的RIE，获得垂直的侧墙 提供金属层之间的连接 * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 除去光刻胶 * Tungsten Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug TiN和钨淀积 TiN和钨淀积 同第一层互连 * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug 钨和TiN抛光 钨和TiN抛光 同第一层互连 * Trench Oxide Polysilicon Cross Section N- Well P- Well N+ Source/Drain P+ Source/Drain Spacer Contact Metal1 Via1 平面视图 完成通孔 * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 Metal2淀积 Metal2淀积 类似于Metal1 厚度和宽度增加，连接更长的距离，承载更大的电流 * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 Photoresist IMD1 W Via Plug Metal2 光刻胶成形 光刻胶成形 相邻的金属层连线方向垂直，减小层间的感应耦合 * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 Photoresist IMD1 W Via Plug Metal2 Metal2刻蚀 Metal2刻蚀 类似于Metal1 * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain