pld运用程序举例文档.docVIP

PLD段码显示 library ieee; use ieee.std_logic_1164.all; entity duanma is port(fff:out bit_vector(1 to 5); aaa:out bit_vector(1 to 5)); end; architecture kk of duanma is begin fff(1 to 5)=11111; aaa(1 to 5)=11111; end; PLD三个数加法编程 library ieee; use ieee.std_logic_1164.all; entity jw is port(in1,in2:in integer range 0 to 15; a,b:out std_logic_vector(1 to 7)); end; architecture gg of jw is signal he:integer range 0 to 45; begin he=in1+in2; with he select a=1111110 when 0|10|20|30|40, 0110000 when 1|11|21|31|41, 1101101 when 2|12|22|32|42, 1111001 when 3|13|23|33|43, 0110011 when 4|14|24|34|44,