MSP430F5529测周法测量信号频率.docVIP

MSP430F5529测量频率 -----测周法 信号变换电路 过零比较器，lm393输出上拉电阻，两电阻分压 程序 #include msp430f5529.h #include stdio.h #include math.h //测周法，在捕获过程中，定时溢出不能被检测出，选择时钟频率为低频时能测出低频，频率高能测出频率高的部分 /* * main.c */ long long start=0; //long long int stop=0; double fre=0.0; unsigned char i=0; unsigned char over=0; void SetVcoreUp (unsigned int level) { // Open PMM registers for write PMMCTL0_H = PMMPW_H; // Set SVS/SVM high side new level SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level; // Set SVM low side to new level SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level; // Wait till SVM is settled while ((PMMIFG SVSMLDLYIFG) == 0); // Clear already set flags PMMIFG = ~(SVMLVLRIFG + SVMLIFG); // Set VCore to new level PMMCTL0_L = PMMCOREV0 * level; // Wait till new level reached if ((PMMIFG SVMLIFG)) while ((PMMIFG SVMLVLRIFG) == 0); // Set SVS/SVM low side to new level SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level; // Lock PMM registers for write access PMMCTL0_H = 0x00; } void init_clock() { SetVcoreUp (0x01); SetVcoreUp (0x02); SetVcoreUp (0x03); UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_7; // Select DCO range 50MHz operation UCSCTL2 = FLLD_0 + 609; // Set DCO Multiplier for 25MHz // (N + 1) * FLLRef = Fdco // (762 + 1) * 32768 = 25MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop __delay_cycles(782000); do { UCSCTL7 = ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Cl