SOPC系统架构与系统生成.pptVIP

SOPC设计技术 SOPC系统架构与系统生成 问题提出: 降低成本、系统复杂度和功耗 Problem: Reduce Cost, Complexity Power 各个FPGA提供商的SOPC解决方案 Xilinx Virtex 4 or Virtex 5 PowerPC硬核、MicroBlaze EDK Altera Cyclone II or Stratix II/III Nios II SOPC Builder NiosII IDE Lattice Lattice Micro32 Actel ARM7、Cortex-M3 以Altera公司的SOPC解决方案为例 器件 Cyclone Cyclone II Cyclone III Stratix Stratix II Stratix III Stratix IV CPU Nios II 32位处理器软核（32 bits Soft Core） FPGA开发环境 Quartus II 以Altera公司的SOPC解决方案为例 系统构建软件 SOPC Builder NiosII软件开发环境 Nios II IDE GNU GCC工具链 IP MegaCore Nios II是什么？ Altera’s 第二代软核32位RISC微处理器 Altera自主开发 Harvard 架构 Royalty-Free FPGA 硬件设计流程 FPGA 硬件设计流程 开发套件, Stratix Cyclone 版本 标准设计框图 Nios II 系统架构 Nios II 框图 Nios II 处理器架构 Nios II 处理器可 版本 Nios II 处理器 提供 三种 ISA 兼容版本 软件： 二进制代码兼容 CPU版本更换不需要更改程序代码 二进制代码兼容 / 性能可伸缩 硬件乘法加速 Nios II Economy version – 无硬件乘法器 使用 GNUPro 数学库 软件实现乘法 Nios II Standard - Full Hardware Multiplier 32 x 32 ? 32 in 3 Clock Cycles if DSP block present, else uses software only multiplier Nios II Fast - Full Hardware Multiplier 32 x 32 ? 32 in 1 Clock Cycles if DSP block present, else uses software only multiplier 硬件乘法器支持 Stratix and Stratix II DSP Blocks Cyclone II Multiplier Blocks Multiplication using 18 x 18 Multiplier Block Optional LE Implementation Enables HW multiplier support for Cyclone Device Family Can also use in Stratix and Stratix II instead of DSP Blocks Mul, Shift, Rotate (~ 8 Clocks Per Mul) Eliminates need for DSP blocks for Nios II MUL NiosII使用许可 Nios II Delivered As Encrypted Megacore Licensed Via Feature Line In Existing Quartus II License File Consistent With General Altera Megacore Delivery Mechanism Enables Detection Of Nios II In Customer Designs (Talkback) No Nios II Feature Line (OpenCore Plus Mode) System Runs If Tethered To Host PC System Times Out If Disconnected from PC After ~ 1 hr Nios II Feature Line (Active Subscriber) Subscription and New Dev Kit Customers Obtain Licenses From Nios II CPU RTL Remains Encrypted Nios II Source License Available U