第十章-可测性DFT.pptVIP

第十章 可测试性设计 Outlines Overview of IC Testing Fault Modeling Automatic Test Pattern Generation (ATPG) Design-for-test (DFT) techniques Scan chain technique MBIST Boundary Scan Verification vs. Test Verification Verifies correctness of design. Performed by simulation, hardware emulation, or formal verification, etc. Performed once prior to manufacturing. Responsible for quality of design. Test Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices. Testing Principle Three basic element A known input Stimulus A known state A known expected response Automatic Test Equipment (ATE) Overview of IC Testing Test Challenges Reduce the cost of test Reduce the vector data size Reduce the tester sequencing complexity Reduce the cost of test equipment Reduce the test time Increase the defect coverage How many function test patterns can cover all the devices? Outlines Overview of IC Testing Fault Modeling Automatic Test Pattern Generation (ATPG) Design-for-test (DFT) techniques Types of Test Vector Sets Exhaustive Apply every possible input vector A long time! Functional Test every function of the device How to guarantee the coverage? Fault Model Derived Find a test for every “modeled” fault Industry practice currently Why Model Faults? Fault model identifies target faults Fault model makes analysis possible Effectiveness measurable by experiments Defect Fault Modeling Definition Defect: Physical abnormally fabricated die E.g. missing/extra material Fault: behavior difference due to a defect E.g. input stuck-at ‘1’, output slow-to-rise Error: machine failure due to a fault E.g. system functional failure Bug – functional failure caused by design problem E.g. system functional failure Example Fault Models Fault models are typically defined on a struc