东南大学soc10 芯片验证.pptVIP

观察仿真波形（续） 看DMAC模块的接口信号波形 如果是存储器到外设的传输 看存储器的接口信号 看相应外设的接口信号 SSI 观察调试信息 如何把C代码中打印的调试信息打印到VCS仿真运行的控制台中？ 在SoC芯片的顶层文件中例化Tube模块，作为一个AHB slave设备，设占用的地址为0x1100c000。 Tube模块接收往0x1100c000地址所写的字符并保存到log文件中。 在arm测试代码中的retarget.c文件实现print函数，print函数把要打印的调试信息发送到0x1100c000 地址 则arm代码调用print函数，即可把调试信息打印到VCS仿真运行的控制台中。 Verification Alternatives Simulation FPGA Prototyping Formal Verification Prototyping Imitating the function of another system to achieve the same results as the imitated system. Usually, the prototyping hardware comprises FPGA’s. More than 10000 times faster than simulation. Simulation Prototyping Prototyping Pros Higher clock rate (up to ~100M cycles/sec) due to specific design of prototyping board. Components as well as the wiring can be customized for the corresponding application. Can be carried along. Cons Not flexible for design change (Every new prototype requires a new board architecture. / Even a small change requires a new PCB.) A Prototyping Example FPGA验证 FPGA选型 FPGA设计步骤 FPGA软件开发工具 FPGA电路板 结果观察 FPGA选型 Altera于1983年创立 ，是可编程芯片逻辑解决方案倡导者 。目前，Altera的全球市场份额已排在第二位，仅次于Xilinx Altera产品系列 Altera目前的FPGA产品有Stratix系列（IV）、Arria系列（II）、Cyclone 系列（III） STRATIX II 系列(90-nm) （EP2S90、EP2S130） STRATIXIII系列（EP3S150）(65-nm ) SoC芯片验证 目录 Why Verification Verification Alternatives What is Design Verification? for (i = 0; i d; i= i+2) { if (y 3) p = p * 3; else q = q + r; } always (posedge clk) begin if (rst==1b1) cnt = sv; else if (cnt==2b00) cnt = 2b01; else if (cnt==2b01) cnt = 2b10; else if (cnt==2b10) cnt = 2b11; else cnt = sv; end Bottom line: to fix as many bugs in your design as possible Verification takes ~ 70% of resources in today’s IC design 设计验证verification的目的是确认设计的功能正确性和性能（速度和功耗等）满足设计要求，贯穿于设计的整个过程 RTL GDSII Gate Design Implementation Physical Implementation RTL GDSII Gate Design Creation Design Flow Functional Specification Where are the Bugs? Functional specification system or behavior-level