高性能并行比特变换运动估计硬件架构设计.pdfVIP

第33 卷第3 期 电 子 与 信 息 学 报 Vol.33No.3 2011 年3 月 Journal of Electronics Information Technology Mar.2011 高性能并行比特变换运动估计硬件架构设计 陈运必*① 郭 立① 李正东② 池凌鸿① ①(中国科学技术大学电子科学与技术系 合肥 230027) ②(重庆通信学院电子技术教研室 重庆 400035) 摘 要：为了满足便携式实时全高清视频的处理要求，该文基于1 维源像素线性阵列，提出一种新的多宏块并行比 特变换运动估计结构，克服以往2 维阵列消耗资源较多且延时大的不足。该文结构易于并行扩展且更为节约资源， 进一步还针对脉动胞元和数据存储器这两个系统瓶颈进行优化设计。FPGA 实现结果表明，与同类设计相比，该 文设计在面积和速度上均有改善，LUTs 资源节约43%，DFFs 资源节约25%，BRAMs 数目节约75%，性能提升 32%。 关键词：运动估计；比特变换；硬件架构；并行处理；脉动阵列 中图分类号：TN47 文献标识码： A 文章编号：1009-5896(2011)03-0717-06 DOI: 10.3724/SP.J.1146.2010.00636 An Efficient Parallel Architecture for One-bit Transform Based Motion Estimation ① ① ② ① Chen Yun-bi Guo Li Li Zheng-dong Chi Ling-hong ① (Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China) ② (Staff room of Electronic and Technology, Chongqing Communication College, Chongqing 400035, China) Abstract: In order to meet the processing requirements of portable real-time full HD video compression, this paper proposes a novel macroblock-level parallel architecture based on 1-D source pixels based linear array, which overcomes the problem of massive amount of resources and large delay caused by 2-D arrays used in literatures. The proposed architecture is easy to extend and area-economical. Furthermore, towards the system bottlenecks, systolic cell and data memory organization, optimized structure are presented. Compared with the traditional architecture, the