数据选择器,译码器.docVIP

用when-else语句编写4选1的数据选择器。 library ieee; use ieee.std_logic_1164.all; entity mux4a is port(a,b,c,d:in std_logic; s:in std_logic_vector(1 downto 0); y:out std_logic); end entity; architecture fl of mux4a is begin y=a when s=00 else b when s=01 else c when s=10 else d ; end architecture fl; 用when-else语句实现具有低电平哟小的8选1数据选择器。、 library ieee; use ieee.std_logic_1164.all; entity mux8a is port(d0,d1,d2,d3,d4,d5,d6,d7:in std_logic; a:in std_logic_vector(2 downto 0); y:out std_logic); end entity mu