EDA技术应用课程讲义实用数字钟系统设计.pptVIP

* 2选1多路选择器VHDL程序 ENTITY mux21a IS PORT( a, b : IN BIT ; k : IN BIT; c : OUT BIT ) ; END ENTITY mux21a ; ARCHITECTURE one OF mux21a IS BEGIN c = a WHEN k = ‘1 ELSE b ; END ARCHITECTURE one ; * 状态机程序 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY zhuantaiji IS PORT ( CLK 0,reset: IN STD_LOGIC; y : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END zhuantaiji; * 状态机程序 ARCHITECTURE behav OF zhuantaiji IS TYPE states IS (st0, st1, st2, st3,st4); SIGNAL stx : states ; BEGIN COMREG : PROCESS(CLK,RESET) BEGIN --决