EDA课后问题详解(适用于朱正伟《EDA技术及应用》).docVIP

实用 文案 1.1、设计集成计数器74161，设计要求如下： 4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear Note Inputs： CLK LDN CLRN D C B A Outputs：QD QC QB QA RCO *RCO = QD QC QB QA Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt4 is port( clk,LDN,CLRN : in std_logic; d,c,b,a : in std_logic; carry : out std_logic; qd, ); end; architecture a of cnt4 is signal data_in: std_logic_vector(3 downto 0); begin data_in=dcba; process(data_in,clk,ldn,clrn) variable cnt:std_logic_vector(3 downto 0); begin