VHDL仿真实现串口接收.doc

FPGA 作业 序号：3 北京信息科技大学，研1505班，刘鹏成 内容：VHDL仿真实现串口接收。 接收文件 ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity uart_receiver is generic(integer_bit :integer:=8); Port (clock_8 : in std_logic; data_uart_litera : in std_logic; reset : in std_logic); end uart_receiver; architecture Behavioral of uart_receiver is signal idle : std_logic :=0; signal state : std_logic_vector (3 downto 0):=0000; signal reg_before : std_logic :=0; signal reg_rfall : std_logic :=0; signal count : std_logic_vector (7 downto 0):=(others=0); signal counter_en : std_logic :=0; signal receiver : std_logic :=0; signal dout : std_logic_vector(7 downto 0):=(others=0); signal dout_8_valid : std_logic_vector(7 downto 0):=(others=0); signal check_bit : std_logic:=0; signal counter_half : std_logic_vector(15 downto 0) :=(others =0); signal clock_half : std_logic :=0; signal conv_bit: std_logic_vector(15 downto 0) :=(others =0); signal sign_bit :std_logic:=0; signal sample_bit:std_logic:=0; component counter is port(num : buffer std_logic_vector (integer_bit-1 downto 0); counter_en : in std_logic; clk_8 : in std_logic); end component; begin counter_1 : counter port map(num = count, counter_en = counter_en, clk_8 = clock_8); conv_bit =conv_std_logic_vector(integer_bit,16); counter_half =0 conv_bit(15 downto 1); process(clock_8) begin if(reset=1) then --高电平复位,异步复位 receiver =0; reg_rfall=0; reg_before=0; elsif(rising_edge(clock_8)) then reg_rfall = (reg_before)and(not data_uart_litera); reg_before = data_uart_l