VHDL语言各种分频器的设计解析.pptVIP

专题二. 经典模块设计;专题内容：;1. 分频器的原理;2. 二进制分频器的设计;二进制分频器的VHDL源程序;Architecture a of fdiv is signal cnt: std_logic_vector(N-1 downto 0); Begin process(clkin) begin if(clkinevent and clkin=1) then cnt = cnt+1; end if; end process; clkout = cnt(N-1); End a;;仿真结果;3. 偶数分频器的设计;偶数分频器的VHDL源程序(1);Architecture a of fdiv is signal cnt: integer range 0 to n-1; Begin process(clkin) --计数 begin if(clkinevent and clkin=1) then if(cntn-1) then cnt = cnt+1; else cnt = 0; end if; end if; end process; process(cnt) --根据计数值，控制输出时钟脉冲的高、低电平 begin if(cntn/2) then clkout = 1; else clkout = 0; end if; end process; End a;;偶数分频器的VHDL源程序(2);Architecture a of fdiv is signal cnt: integer range 0 to n/2-1; signal temp: std_logic; Begin process(clkin) begin if(clkinevent and clkin=1) then if(cnt=n/2-1) then cnt = 0; temp = NOT temp; else cnt = cnt+1; end if; end if; end process; clkout = temp; End a;;仿真结果;4. 奇数分频器的设计;奇数分频器的VHDL源程序;architecture a of fdiv is signal cnt1, cnt2: integer range 0 to N-1; begin process(clkin) begin if(clkin‘event and clkin=’1‘) then --上升沿计数 if(cnt1N-1) then cnt1 = cnt1+1; else cnt1 = 0; end if; end if; end process;; process(clkin) begin if(clkin‘event and clkin=’0‘) then --下降沿计数 if(cnt2N-1) then cnt2 = cnt2+1; else cnt2 = 0; end if; end if; end process; clkout = 1 when cnt1(N-1)/2 or cnt2(N-1)/2 else 0; end a;;仿真结果;5. 占空比可调的分频器的设计;占空比可调的分频器VHDL源程序;architecture a of fdiv is signal cnt: integer range 0 to n-1; begin process(clkin) begin if(clkinevent and clkin=1) then if(cntn-1) then cnt = cnt+1; else cnt = 0; end if;