元器件样本专辑116册电子元件-170m-版mz_c10.pdfVIP

Figure 10-0. Listing 10-0. Table 10-0. The processor’s SDRAM interface enables it to transfer data to and from synchronous DRAM (SDRAM) at 2xCLKIN. The synchronous approach coupled with 2xCLKIN frequency supports data transfer at a high throughput—up to 240 Mbytes/sec. All inputs are sampled and all out- puts are valid at the rising edge of the clock SDCLK. The processor’s SDRAM controller provides a glueless interface with stan- dard SDRAMs and supports: • 16M, 64M, and 128M SDRAMs and x4, x8, x16, or x32 configu- rations. You can connect up to eight x4 (excluding 128M devices), four x8, two x16, or one x32 SDRAM to the processor’s external port, ADDR23-0 bus. • Up to 16 Mwords of SDRAM in external memory. • Zero wait state, 60 Mwords/sec. with some access types. • Full page burst length only for page read and write operations. • SDRAM page sizes of 1024, 512, and 256 words. • A programmable refresh counter to coordinate between varying clock frequencies and the SDRAM’s required refresh rate. • Buffering for multiple SDRAMs connected in parallel. • Shared SDRAM devices in a multiprocessing system. ADSP-21065L SHARC User’s Manual 10-1 • A separate A10 pin that enables applications to precharge SDRAM before issuing a refresh command. • Connection to any one of the processor’s external memory banks. • Self-refresh, low-power mode. • Two power-up options. Figure 10-1 shows a block diagram of the processor’s SDRAM interface. In this uniprocessor example, the SDRAM interface connects to four 1M×8×2 SDRAM devices to provide applications, in effect, use of 2M of 32-bit words. The same address and control bus feeds all four SDRAM devices.