模100计数器源程序.docxVIP

仿真程序： library IEEE; use IEEE. STD LOGIC 1164. ALL; use IEEE. STDLOGICARITIL ALL; use IEEE. STDLOGICUNSIGNED. ALL; entity exp5l port (elk :rst entity exp5l port ( elk : rst data datasel )； out in in STDLOGIC; STDL0GIC; out STDLOGICVECTOR(7 downto 0); inout STDL0G【CVECT0R(3 downto 0) end exp5l; circhitecture Behavioral of exp5l is signal divclk STDLOGICVECTOR(1 downto 0); signal digit I STDL0GICVECT0R(3 downto 0); signal digit2 :signal data4 : signal digit2 : signal data4 : signal firstover signal sei : signeil clkl : STDL0GICVECT0R(3 downto 0); :STD LOGIC; STDL0GIC; STDL0GIC; begin datsel(3 dow