数字电路教学课件：chapter5-5.pptVIP

A Guide to Verilog HDL for Sequential Circuit gsu@hust.edu.cn Introductory information 3’b101 width’base formatnumber parameter BIT=1, BYTE=8,PI=3.1415926; ‘define (global) reg [3:0] Counter; reductions operator(缩位) e.g., A=4’b1010, ^A=A[0]^A[1]^A[2]^A[3]=1’b1;A=0 Concatenation operators(位拼接) e.g., A=1’b1,C=2’b10, Y={A,C}=3’b110 Introductory information (cont.) module module_name(ports) ports declaration; parameter; data type definitions; behavior description endmodule Introductory information (cont.) Blocking Assignment Statement = Non-Blocking Assignment Statement