数字电路教学课件：chapter4-4.pptVIP

Flip-flops Chapter4 MSI Synchronous counter SN74xx163 4-bit binary Parallel load capability Active low clear LD : preset CLR : clear ENP ENT : input enable signal that control counting RCO : carry-out(0-1) MSI Synchronous counter Modulo-16 counter Modulo-N counter N16 N16 N divided by 16 is 0. Modulo-(60)10 counter Step1 : 74ls163 modulo-10 counter 0--9 Step2: 74ls163 modulo-6 counter 0--5 Step3: connect two parts Analysis The modulo-6 counter count up every 10 clock pulse which is presented to modulo-10. The active clock pulse is positive edge. The modulo-10 counter CLR=(QDQA)’ The CLR