SSD2832G24芯片详细规格书1.4.pdfVIP

SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD2832 Advanced Information MIPI CD-PHY Tx Bridge Chip This document contains information on a new product. Specifications and information herein are subject to change without notice. SSD2832 Rev 1.4 P 1/184 Mar 2019 Copyright  2019 Solomon Systech Limited APPENDIX: IC REVISION HISTORY OF SSD2832 SPECIFICATION Version Change Items Effective Date st 22-Sep-17 1.0 1 Release 1.1 1. Modified the following pin assignment 18-Oct-17 H19 changed from NC to VSS H20 changed from NC to VSS B14 changed from NC to Data0_12 H18 changed from HSYNC2 to NC A1 changed from HSYNC3 to NC H8 changed from VSYNC3 to NC D22 changed from VSYNC 2 to NC K16 changed from DEN2 to NC E6 changed from DEN3 to NC A2 changed from PCLK3 to NC E10 changed from PCLK2 to NC H2 changed from DATA0_60 to NC H1 changed from DATA0_61 to NC J3 changed fromDATA0_62 to NC K2 changed from DATA0_63 to NC N1 changed from CSX1 to NC 2. changed TX0_B1 to TXA_B1 1.2 1. Added 4 lane mode in 0xDE 02-Mar-18 2. Revised 0xBA bit[15:14] from PEN to FR 3. Added mipi timing description on local(APB) register CPHY_TX_GR1 4. Added mipi timing description on local(APB) regis