数字逻辑7-2.pptVIP

Cascade of two D latches : master and slave;They are enabled in complementary times ! D flip-flop CLK=0, master enable, slave hold ; input come in ;CLK=1, master hold, slave enable ; input cut off. The state output can be changed only at the positive edges of CLK and get the value of input at that time (trigger time) ! Control relation for D flip-flop The setup time of the master latch is divided to the setup time and hold time of flip-flop ! Time delay in D flip-flop Negative-edge-triggered D flip-flopThe state changed at the negative edges of CLK ! Other kind of D flip-flop D flip-flop w