优秀毕业论文：VHDL语言的UART串行接口芯片设计程序清单.docVIP

VHDL语言的UART串行接口芯片设计程序清单附录1 数据接收据器的VHDL语言描述清单LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;use ieee.std_logic_signed.all; ENTITY UART_receiver ISPORT(RxD, Bclkx8, sysclk, reset, RDRF:IN STD_LOGIC;?????? RDR:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);?????? setRDRF, setOE, setFE:OUT STD_lOGIC);END UART_receiver; ARCHITECTURE rtl OF UART_receiver IS TYPE stateTYPE IS (R_WAiT, START_DETECTED,R_DATA);SIGNAL state, nextstate:stateTYPE;SIGNAL RSR:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL cnt1:INTEGER RANGE 0 TO 7;SIGNAL cnt2:INTEGER RANGE 0 TO 8;