基于CPLD的频率计的设计与实现.docVIP

基于CPLD的频率计设计 摘 要 频率计是一种基本的测量仪器。它被广泛应用航天、电子、测控等领域。复杂可编程逻辑器件（CPLD）具有集成度高、运算速度快、开发周期短等特点，它的出现，改变了数字电路的设计方法增强了设计的灵活性。于此，本文提出了一种CPLD的数字频率计的设计方法。该电路简洁，软件潜力得到充分挖掘，低频段测量精度高，有效防止了干扰的侵入Max+plusII上编译仿真后使结果更加清晰，波形测试点读数精确，参数调节方便。因此软件仿真设计可以节省设计资源，减少设计步骤，缩短设计周期。 关键词：Frequency meter is a basic measuring instrument, and measuring electronics are the most basic one of the measurements. Because the strong anti-jamming is easy to transport, so the measurement accuracy of frequency signals can be higher. It is so widely used in aerospace, electronics, measurement and control fields and so on. Complex programmable logic device (CPLD) has the of characteristics of highly integrated, high computing speed, shorter development cycle and so on, the appearance of it changs the methods of digital circuit design, and enhances design flexibility. In view of this, this paper produces a CPLD-based digital frequency meter’s design method. This design’s circuit is simple, software’s potential is fully tapped and low-frequency measurements have high accuracy, effectively preventing the intrusion of the interference. The experimental results from the point of view, the use of CPLD design of electronic circuits can make up for the traditional hardware designing electronic circuit’s deficiencies. Some simulation results can not be completed in the hardware design, but can be achieved in software design, this is the greatest advantages of the CPLD design. At the same time, the procedures can compile on the EDA software platform-Max+plusII, so that the results after the simulation are even more clear, readings of test point waveforms are accurate, parameters are adjusted facilitatily. Therefore the software simulation design can save resources, reduce design steps and shorten the design cycle. Key words: Frequency meter; EDA technology; CPLD;目 录 摘 要 I Abstract II 目 录 III 第一章 绪 论 1 1.1 基于CPLD的频率计系统设计工程背景 1 1.2 频率计设计的目的和意义 2 1.2.1 频率计设计的目的 2 1.2.2 频率计设计的意义 2 1.3 论文所做的工作及研究内容 3 第二章 设计环境介绍 5 2.1 EDA技术