基于DSP和FPGA的图像处理系统设计本科生毕业设计.docVIP

中文题目：基于DSP和FPGA的图像处理系统设计 外文题目：IMAGE PROCESSING SYSTEM DESIGN BASED ON DSP AND FPGA 摘要 本文研究了以TI高性能DSP为核心处理器的视频实时图像处理系统的设计原理与组成，并基于DSP + FPGA架构实现了视频图像处理系统。本图像处理系统主要由图像采集电路、图像处理电路、显示电路以及系统软件组成。 首先经过CCD图像传感器采集复合视频信号，经过视频AD处理器SAA7115)转换成8 bit的数字信号，通过DMA方式存放在双口RAM中，该处理器同时还输出像素时钟信号PCLK)，场同步CS)、行同步HS)、奇偶场OE)、复合消隐信号BLANK)。 数字信号处理器DSPTMS320VC5501)是本处理器的核心部分，其功能是完成整个系统的图像预处理以及数据流存储时序控制等功能。经过DSP处理后输出8 bit的数字视频信号以及像素时钟信号PCLK)、场同步CS)、行同步HS)，一起送FPGA产生视频信号的时序逻辑，然后送视频DA处理器SAA7105H )，最后通过VGA视频接口输出。静态双口RAM用于存储图像数据的，图像数据的读写控制时序通过DSP来实现。视频DA处理器SAA7105H)将FPGA输出的数字视频信号、像素时钟、行场同步信号合成为彩色全电视信号然后通过VGA输出。 关键字：DSP；FPGA；图像处理；电路设计；系统软件 Abstract This paper studies the system design principle and composition the of TI high performance DSP core processor for real-time video image processing , and it can achieve video image processing system based on the architecture of DSP and FPGA. The image processing system is composed of image acquisition circuit, image processing circuit, display circuit and system software. After the first CCD image sensor collect the composite video signal, the video A/D processor (SAA7115) is converted into a digital signal of 8 bit, which is stored in dual-port RAM through DMA, the processor also outputs pixel clock signal (PCLK), field synchronization(CS), synchronous (HS), parity field (OE), composite blanking signal (BLANK). DSP digital signal processor (TMS320VC5501) is the core part of this processor, its function is to complete the whole system of image preprocessing and the sequence of data storage control . After DSP treatment, the output of the 8 bit digital video signal and a pixel clock signal (PCLK). The field synchronization (CS), synchronous (HS), which is send to FPGA for producing video signals, then transmitted to the video processor D/A (SAA7105), the final output through a VGA video. Static double port RAM is used to store the image data, the timing control of image data read and writed is realized by DSP. Video D/A processor (SAA7105) com