电子信息工程专业外文翻译--处理器架构.docVIP

外文原文： Processor Architecture This chapter describes the hardware structure of the Nios? II processor, including a discussion of all the functional units of the Nios II architecture and the fundamentals of the Nios II processor hardware implementation. This chapter contains the following sections: ■ “Processor Implementation” on page 2–2 ■ “Register File” on page 2–3 ■ “Arithmetic Logic Unit” on page 2–4 ■ “Reset and Debug Signals” on page 2–8 ■ “Exception and Interrupt Controllers” on page 2–8 ■ “Memory and I/O Organization” on page 2–10 ■ “JTAG Debug Module” on page 2–17 The Nios II architecture describes an instruction set architecture (ISA). The ISA in turn necessitates a set of functional units that implement the instructions. A Nios II processor core is a hardware design that implements the Nios II instruction set and supports the functional units described in this document. The processor core does not include peripherals or the connection logic to the outside world. It includes only the circuits required to implement the Nios II architecture. The Nios II architecture defines the following functional units: ■ Register file ■ Arithmetic logic unit (ALU) ■ Interface to custom instruction logic ■ Exception controller ■ Internal or external interrupt controller ■ Instruction bus ■ Data bus ■ Memory management unit (MMU) ■ Memory protection unit (MPU) ■ Instruction and data cache memories ■ Tightly-coupled memory interfaces for instructions and data ■ JTAG debug module Processor Implementation The functional units of the Nios II architecture form the foundation for the Nios II instruction set. However, this does not indicate that any unit is implemented in hardware. The Nios II architecture describes an instruction set, not a particular hardware implementation. A functional unit can be implemented in hardware, emulated in software, or omitted entirely. A Nios II implementation is a set of design choices embodied by a particular Nios II processor core. All implem