虚拟化技术Virtualization Technique.pptVIP

虛擬化技術Virtualization Technique System Virtualization Memory Virtualization Agenda Basic concept of memory management Brief introduction to ARM v7 AMSA Memory Virtualization Shadow page table Hardware assistance Comparison Basic concept of memory management Memory Management Unit A hardware component responsible for handling accesses to memory requested by the CPU Address translation: virtual address to physical address (VA to PA) Memory protection Cache control Bus arbitration Page tables are maintained by operating system, and MMU only references them. TLB updates are performed automatically by table walking hardware Page Tables A page table is the data structure used by a virtual memory system to store the mapping between virtual addresses and physical addresses Translation table base register(TTBR) Also called page table base register A register that stores the address of the base page table for MMU TLB Translation look-aside buffer A CPU cache that memory management hardware uses to improve virtual address translation speed The TLB is typically implemented as content-addressable memory (CAM) The CAM search key is the virtual address and the search result is a physical address Brief introduction to ARMv7 VMSA ARMv7 VMSA VMSA: Virtual memory system architecture Support four mapping types 16MB Super section 1MB Section 64KB Large page 4KB Small page Basically a 32-bit two-layer translation table Other features (virtualization extension and 64-bit large physical address extension) would be mentioned in the future class L1 Page Table First-level table Translation properties for a Section and Super-section Translation properties and pointers to a second-level table for a Large page or a Small page. L1 descriptor[1:0] 0b00, invalid or fault entry Translation fault 0b01, page table Address of 2nd level translation table 0b10, section of super-section 0b11, special usage with PXN attribute 1st Page Table Descriptor L2 Page Table Second-level tables The base address and t