步行街道交通等控制电路设计.docVIP

步行街道交通等控制电路的设计 设计者：陈丹（0811020215） 余建均（0811020221） 整体结构图 电路模块设计：包含三部分去抖模块、计数模块、交通控制模块 去抖模块 模块的语言设计 DITHER（去抖模块）VHDL源程序 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY DITHER IS PORT(UPIN: IN STD_LOGIC; DOWNIN:IN STD_LOGIC; KEYOUT:OUT STD_LOGIC); END DITHER; ARCHITECTURE BEHAVE OF DITHER IS SIGNAL OUT1: STD_LOGIC; SIGNAL OUT2: STD_LOGIC; BEGIN OUT1=NOT(OUT2 AND UPIN); OUT2=NOT(OUT1 AND DOWNIN); KEYOUT=OUT1; END BEHAVE; （2）设置计数模块 COUNT（计数模块）VHDL源程序 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY COUNT IS PORT(CLK: IN STD_LOGIC; CLEAR: IN STD_LOGIC; CLKADD: IN STD_LOGIC; CLKSUB: IN STD_LOGIC; PRE_SET: IN STD_LOGIC; HUMAN_SET: IN STD_LOGIC; RST: IN STD_LOGIC; GHUMAN_TIME: OUT INTEGER RANGE 31 DOWNTO 0; GHUMAN_CLKT: OUT INTEGER RANGE 31 DOWNTO 0; GVEHICLE_TIME:OUT INTEGER RANGE 31 DOWNTO 0); END COUNT; ARCHITECTURE BEHAVE OF COUNT IS SIGNAL HUMAN_TIME: INTEGER RANGE 31 DOWNTO 0; SIGNAL VEHICLE_TIME: INTEGER RANGE 31 DOWNTO 0; SIGNAL SSTATE: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL SCLK: STD_LOGIC; SIGNAL DSCLK: STD_LOGIC; BEGIN PROCESS(CLK) SSTATE=000WHEN PRE_SET=0 ELSE HUMAN_SET CLEAR CLKSUB; SCLK=CLKADD OR CLKSUB OR CLEAR; BEGIN IF (CLKEVENT AND CLK=1)THEN DSCLK=SCLK; END IF; END PROCESS; PROCESS(RST,CLEAR,DSCLK) BEGIN IF(RST=1)THEN VEHICLE_TIME=8; ELSIF(DSCLKEVENT AND DSCLK=1)THEN CASE SSTATE IS WHEN 0100=VEHICLE_TIME=0; WHEN 0101=VEHICLE_TIME=0; WHEN 0110=VEHICLE_TI