静电防护设计原理与方法.pptVIP

静电防护设计原理与方法 静电防护设计原理与方法 11.1 元器件防护设计 11.2 印制电路板组件防护设计 11.3 电子整机系统的防护设计 11.1 元器件防护设计 Design Concepts Thick Field Device Main Design Parameters of the FOD Drain contact nMOS Transistors (FPDs) essentially thin oxide devices as opposed to the FOD are also called field-plated diodes or gated-diodes used as a primary protection device, in technologies with feature sizes greated than 1μm Main design parameters of nMOS and layout HBM ESD performance in FPDs as a function of DCG Gate-Coupled nMOS (GCNMOS) GCNMOS ESD Failure Distribution GCNMOS GCNMOS I/O Applications SCR Protection Device MLSCR (modified LSCR) Design and layout of the SCR devices layout ESD protection design synthesis Secondary Protection Devices protection scheme Con. total input protection inputs with polysilicon resistor polysilicon resistor reliability 尽量减小环路面积 尽量减小环路面积 尽量缩短线条长度 使静电防护器件远离其他静电敏感器件 尽量使敏感器件和连线远离非接地的金属体 在静电防护工作中值得注意的几个问题 关于静电泄放棒(球) 关于无线防静电腕带 尽量缩短线条长度 * 输入端的防护设计 Will shunt most or all of the current during an ESD event Can be: a thick field transistor a silicon controlled rectifier(SCR) a nMOS transistor a simple pn diode Serves to limit the voltage or current at the circuit being protect until the primary device is fully operational. Can be: a small grounded gate MOS transistor a diode between the pads and the power/ground supplies Can be: polysilicon n+ diffusion p+ diffusion n-well --thick oxide or field oxide device (FOD) --used for technologies with feature sizes (ranging from 3μm to 1μm) Three Different cross-sections HBM failure thresholds increase as the channel length is decreased in the 7μm to 2μm range Increased-saturate: reason: distance between the heat source and the contact (contact close to diffusion edge—the produced heat spread to heat the contact metalization—result in a lower failure voltage) Impact of the contact spacing: very important for the abrupt junction processes, weak effect for lightly doped drain (LDD) the effect virtually vanishes for silicide