高速视频处理系统的信号完整性分析.docVIP

更多电子资料请登录 高速视频处理系统的信号完整性分析* 邓集杰 刘铁根 褚 备 张忠传 (天津大学精仪学院光电信息技术科学教育部重点实验室510.1010 SI analysis of the high-speed video processing system Deng Jijie Liu Tiegen Chu Bei Zhang Zhongchuan (College of Precision Instrument and Opto-Electronics Engineering, Tianjin University, Key Laboratory of Opto-electronicsInformation and Technical Science(Tianjin University), Ministry of Education, Tianjin, 300072) Abstract: In high-speed video processing system, there are three mainly problems about signal Integrity (SI) in: reflection, crosstalk and delay. the system’s impedance characteristic was calculated by means of transmission line model analysis. Based on the theory that impedance characteristic of transmission line must match that of load, it was presented what the termination resistant would be used to series in high-speed bus to reduce reflection and crosstalk of high-speed bus. It was simulated that reflection and crosstalk of high-speed bus’s signal waveform. Based on IBIS model, delay characteristic was analyzed. It turned out that series termination resistant is an effective way to reduce the reflection and crosstalk and satisfies requirement of timing. Next, it is determined that layout rule about SI based on simulation results, and design proposal on layout. Simulation after layout and measured results meet the requirements of SI. Keywords: SI; signal simulation; video processing system; IBIS model 1 引 言 随着数字电路信号速度的提高, 信号完整性问题的影响也愈加突出[1]。信号完整性(signal integrity)简称SI, 指信号从驱动端经过传输线到达接收端的波形的完整程度, 其主要包括3个方面—— 反射、串扰和延时问题[2]。 在分析高速视频处理系统的信号完整性问题基础上, 采用端接电阻的方法减少反射与串扰, 通过仿真表明该方案不仅能有效减少反射与串扰, 还能够满足系统的时序要求, 并确定了系统电路板的设计方案, 布线后仿真和电路板的实测结果均可满足信号完整性的要求。 2 信号完整性分析 2.1 高速视频处理系统构成 在实验室自行开发的视频处理系统中, 以DSP作为系统的中央控制单元, 用于数据的处理、传输和对接口的控制, 两块Flash芯片用于存储源程序代码、算法模板以及数据库。SDRAM用来补充DSP片内有限的存储资源, 提供高速大容量的外部数据存储空间。DSP选用TMS320DM642。图1是EMIF模块和SDRAM的电路方案。 图1 EMIF模块和SDRAM的电路结构 Fig. 1 Connection between EMIF Module and SDRAM 系统设计的难点在于DSP与SDRAM的通信部分, 其中SDRAM的最高频率可以达到166 MHz, 在DSP的EMIF的限制下仍