基于CPLD频率计设计.doc

内蒙古科技大学 本科生毕业设计说明书（毕业论文） 题 目：基于CPLD的频率计设计 学生姓名：李 松 学 号：200540503314 专 业：测控技术与仪器 班 级：测控05-3班 指导教师：燕芳 讲师基于CPLD的频率计设计 摘 要 频率计是一种基本的测量仪器，频率测量是电子学测量中最为基本的测量之一。由于频率信号抗干扰性强，易于传输，因此可以获得较高的测量精度。所以它被广泛应用于航天、电子、测控等领域。 复杂可编程逻辑器件（CPLD）具有集成度高、运算速度快、开发周期短等特点，它的出现，改变了数字电路的设计方法，增强了设计的灵活性。鉴于此，本文提出了一种基于CPLD的数字频率计的设计方法。该设计电路简洁，软件潜力得到充分挖掘，低频段测量精度高，有效防止了干扰的侵入。从实验结果上看，采用CPLD设计的电子电路，可以弥补传统硬件电子电路设计中的不足。在硬件设计中不能完成的仿真实验可以在软件设计中实现，这是利用CPLD设计的最大优点。同时程序在EDA软件平台Max+plusII上编译仿真后使结果更加清晰，波形测试点读数精确，参数调节方便。因此软件仿真设计可以节省设计资源，减少设计步骤，缩短设计周期。 关键词：频率计；EDA技术；CPLD； Design of the frequency meter based on CPLD Abstract Frequency meter is a basic measuring instrument, and measuring electronics are the most basic one of the measurements. Because the strong anti-jamming is easy to transport, so the measurement accuracy of frequency signals can be higher. It is so widely used in aerospace, electronics, measurement and control fields and so on. Complex programmable logic device (CPLD) has the of characteristics of highly integrated, high computing speed, shorter development cycle and so on, the appearance of it changs the methods of digital circuit design, and enhances design flexibility. In view of this, this paper produces a CPLD-based digital frequency meter’s design method. This design’s circuit is simple, software’s potential is fully tapped and low-frequency measurements have high accuracy, effectively preventing the intrusion of the interference. The experimental results from the point of view, the use of CPLD design of electronic circuits can make up for the traditional hardware designing electronic circuit’s deficiencies. Some simulation results can not be completed in the hardware design, but can be achieved in software design, this is the greatest advantages of the CPLD design. At the same time, the procedures can compile on the EDA software platform-Max+plusII, so that the results after the simulation are even more clear, readings of test point waveforms are accurate, parameters are adju