基于FPGA数字延迟单元的实现和比较.pdfVIP

34 9 ELECT RON IC M EASU REMEN T TECHN OL OGY 2011 9 FPGA 邱有刚 黄建国 李 力 ( 电子科技大学自动化工程学院 成都 611731) : FP GA ( DDL) 3 , Alt ra Quartus II V rilog H DL IP CORE 3 , Quartus ÒSignalT apÒ, PCB , , , , : ; V rilog H DL; FP GA ; SignalT apÒ : TP2 : A The implementation and comparison of DDL based on FPGA Qiu Yougang H uang Jianguo Li Li ( School of Autom ation Engin ring, U niv rsity of El ctronic Sci n c and T chnology of China, Ch ngdu 611731) Abstract: This pap r has propos d thr m thods to r aliz th digital d lay lin ( DDL) bas d on th f i ld programmabl gat s array( FP GA) and off r d r sp ctiv application scop . W ith th V rilog H DL languag and its IP CORE, w hav nd avor d to apply th s thr m thods. Finally w utiliz d th mb dd d logic analyz r ( SignalT ap Ò) , w hich is provid d by Quartus Ò int grat d d v lopm nt nvironm nt, to t st and v rify all of th m. Th r sults show that all of t h m ar applicabl and th d sign is comparativ ly simply and th modul is stabl and r liabl . Keywords: digital d lay lin ; V rilog H DL ; FPGA; SignalT ap Ò 0 1. 1 1 1 : , [ 8] [ 1] [ 2] , Count r 1 , A D9501, , , , [ 3] , 10 ps , , Count r1 , , , , , ,