JTIDS消息字还原模块的FPGA设计.pdfVIP

Vol. 37, No. 5 37 5 May, 2012 Fire Contr ol Command Control 2012 5 : 1002-0640(2012) 05-0152-04 JTIDS FPGA * 1 1 2 宋家友, 莫新康 , 牛强军 ( 1. , 450001, 2. , 464000) : Link16 , JTIDS , CCSK , CCSK , , RS Link16 , , Q art s II Cyclone II 2 8 208 8 , , EP C Q C FPGA JT IDS JTIDS : , , RS , , : TN919. 3, TN919. 4: A Design of JTIDS Message Restorer Based on FPGA 1 1 2 - , - , - SONG Jia yo M O Xin kang NIU Qiang j n ( 1. Inf ormation E ngineering Institute, Zhengz hou Univ ersity , Zheng z hou 450001, China, 2. The F irst A eronautic Institute of A ir Force, X iny ang 464000, China) : 16 , Abstract According to the p blic Link information criteria one JTIDS message restorer is designed combining w ith the req irements for o r army tactical data link, in w hich s b mod les s ch as CCSK codes decryption, CCSK decoding, deinterleaving, and RS decoding are contained. Based on the principle of Link16 message restorer , the s b mod les are designed and the scheme of hardw are implementation is given. Systemic synthesis and sim lation for the message restorer are accomplished on the Q art s II 2 8 208 8, softw are platform w ith Cyclone II FPGA chip EP C Q C and verification is done on the development board w ith Cyclone II FPGA chip. T he hardware prod ct co ld be sed to test and eval ate the f nction of the data link and so on. Key words: FPGA, Joint T actical Information Distrib tion System(JT IDS) , RS decoding, Cyclic Cod