飞思卡尔后备资料1.pptVIP

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飞思卡尔后备资料1.ppt

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HCS12 Overview 8 16-Bit Microcontroller Division HCS12 Building Blocks HCS12 Documentation Device User Guide MC9S12DP256 Device User Guide (9S12DP256UG/D) [1Mb] HCS12 V1.5 Core User Guide (S12CPU15UG/D) [6Mb] Block User Guides PIM_9DP256 Block User Guide (9S12DP256PIMUG/D) FTS256K Block User Guide (S12FTS256KUG/D) EETS4K Block User Guide (S12EETS4KUG/D) CRG Block User Guide (S12CRGUG/D) ECT_16B8C Block User Guide (S12ECT16B8CUG/D) ATD_10B16C Block User Guide (S12ATD10B16CUG/D) [6Mb] SCI Block User Guide (S12SCIUG/D) SPI Block User Guide (S12SPIUG/D) PWM_8B8C Block User Guide (S12PWM8B8CUG/D) MSCAN Block User Guide (S12MSCANUG/D) VREG Block User Guide (S12VREGUG/D) Watch out for the Rev Number of each Guide - there is a list in the Device User Guide of which rev was appropriate when the device was created. Click here to learn how to receive up-to-date technical documentation Useful Engineering Bulletins EB386 HCS12 D-Family Compatibility Considerations EB376 A comparison of the MC9S12DP256 (mask set 0K36N) versus the HC12 CPU Core(Programming Model) Core Features (1 of 2) ? HCS12 has identical programmers model to M68HC11/M68HC12 No new registers No changes in interrupt stacking order Muxed and non-muxed external interfaces Possible to reuse existing software source code Note: timing loops change due to new clock frequency, Byte counts and instruction cycle times. Almost all peripheral drivers will require updating Performance improvement when using new instructions Reduced interrupt latency Increased math speed Increased performance Instruction Queue data to increase performance Instructions execute faster while remaining deterministic Core Features (2 of 2) HC11 instruction set with extra instructions designed with compilers in mind: ? New instructions and addressing modes to support high level languages.* Added Stack pointer and program counter offset indexed addressing 11 math in