测试平台.pptVIP

运行仿真，查看延迟信息 延时 /~mcdonald/class/ce422/qhdl * 表格式测试程序设计 测试向量 创建测试平台时，测试向量应覆盖所有可能发生的状态。一般可先设计一个测试表格。本例测试向量表如下： 序号 clk rst cnt 1 ‘0’ ‘1’ “0000” 2 ‘1’ ‘1’ “0000” 3 ‘0’ ‘0’ “0000” 4 ‘1’ ‘0’ “0001” 5 ‘0’ ‘0’ “0000” 6 ‘1’ ‘0’ “0010” … … … … … … … … EX4-顶层 EX4-激励与验证模块 entity clk_rst_ver is port ( clk : out std_logic; rst : out std_logic; iCnt : in std_logic_vector(3 downto 0) ); end clk_rst_ver; EX4-激励与验证模块cont. type test_vector is record clk : STD_LOGIC; rst : STD_LOGIC; cnt : STD_LOGIC_VECTOR(3 downto 0); end record; type test_vector_array is array(natural range ) of test_vector; constant test_vectors : test_vector_array := ( -- reset the counter (clk = 0, rst = 1, cnt = 0000), (clk = 1, rst = 1, cnt = 0000), (clk = 0, rst = 0, cnt = 0000), EX4-激励与验证模块cont. -- clock drive counter (clk = 1, rst = 0, cnt = 0001), (clk = 0, rst = 0, cnt = 0001), (clk = 1, rst = 0, cnt = 0010), (clk = 0, rst = 0, cnt = 0010), (clk = 1, rst = 0, cnt = 0011), (clk = 0, rst = 0, cnt = 0011), (clk = 1, rst = 0, cnt = 0100), (clk = 0, rst = 0, cnt = 0100), …… (clk = 0, rst = 0, cnt = 1111), (clk = 1, rst = 0, cnt = 0000), (clk = 0, rst = 0, cnt = 0000), (clk = 1, rst = 0, cnt = 0001“)); EX4-激励与验证模块cont. verify: process variable vector : test_vector; variable errors : boolean := false; BEGIN for i in test_vectorsrange loop vector := test_vectors(i); clk = vector.clk; rst = vector.rst; wait for 20 ns; if icnt /= t then assert false report cnt is wrong value; errors := true; end if; end loop; EX4-激励与验证模块cont. assert not errors report test vectors false severity note; --There is a error assert errors report test vectors pass severity note; --There are right wait; end process verify; 断言语句 断言语句主要用于向用户报告信息，如系统信息和错误信息，在极大测试向量时很有用。 语法： assert 条件 [report 报告信息] [severity 出错等级]; 若条件为真，则不执行该语句，否则报告信息。 报告信息必须为字符串类型 出错等级： note 给用户提示，无错误. 不中断模拟。 warning 警告当前设计有错，暂时不会引起完全失败，如不修改，可能引起后续错误. 不中断模拟。 error