基于VHDL电子表设计.ppt

component counter port( clk,load:in std_logic; buffertime: in std_logic_vector(23 downto 0); time:out std_logic_vector(23 downto 0) ); end component; component alarmreg port( clk,alarmload:in std_logic; buffertime:in std_logic_vector(23 downto 0); alarmtime:out std_logic_vector(23 downto 0) ); end component ; component bell port( clk,houralarmon,alarmon:in std_logic; alarmtime,time:in std_logic_vector(23 downto 0); alarm_signal:out std_logic ); end component; signal buffertime,time,alarmtime:std_logic_vector(23 downto 0); signal iscount,alarmload,timeload:std_logic; begin sm1:statemachine port map(clk,keypressed,functionkey,keyvalue, iscount,alarmload,timeload,buffertime); sm2:statemachine2 port map(clk,keypressed,keyvalue,alarmon,houralarmon); cnt:counter port map(clk,timeload,buffertime,time); reg:alarmreg port map(clk,alarmload,buffertime,alarmtime); bl:bell port map(clk,houralarmon,alarmon,alarmtime,time,alarm_signal); process(iscount,time,buffertime) begin if(iscount=1) then displaytime=time; else displaytime=buffertime; end if; end process; end rt; when modifytime6= if(keypressed=1and keyvalue=1011)then next_state=count; elsif(keypressed=1and functionkey=0)then next_state=modifytime7; time_temp(3 downto 0)=keyvalue; else next_state=present_state; time_temp=time_temp; end if; when modifytime7= if(keypressed=1and keyvalue=1011)then next_state=count; elsif(keypressed=1and keyvalue=1010)then next_state=loadtime; else next_state=present_state; end if; time_temp=time_temp; when loadtime= next_state=count; time_temp=time_temp; when setalarm1= if(keypressed=1and keyvalue=1011)then next_state=count; elsif(keypressed=1and keyvalue=0010)then next_state=setalarm2; time_temp(23 downto 20)=keyvalue; else next_state=present_state; time_temp=time_temp; end if; when setalarm2= if(keypressed=1and keyvalue=1011)then next_state=count; elsif(keyp