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带有并行置位的移动寄存器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SHFRT IS PORT ( CLK，LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC ); END SHFRT; ARCHITECTURE behav OF SHFRT IS BEGIN PROCESS (CLK, LOAD) VARIABLE REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN IF CLKEVENT AND CLK = 1 THEN IF LOAD = 1 THEN -- 装载新数据 REG8 := DIN; ELSE REG8(6 DOWNTO 0) := REG8(7 DOWNTO 1); END IF; END IF; QB = REG8(0); END PROCESS; -- 输出最低位 END behav; 三态门设计 1）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tri_s IS port ( enable : IN STD_LOGIC; datain : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END tri_s ; ARCHITECTURE bhv OF tri_s IS BEGIN PROCESS(enable,datain) BEGIN IF enable = 1 THEN dataout = datain ; ELSE dataout =ZZZZZZZZ ; END IF ; END PROCESS; END bhv; 2）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tristate2 IS port ( datain3, datain2, datain1, datain0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END tristate2 ; architecture body_tri of tristate2 is begin q = datain1 when ctl=00 else (others =Z) ; q = datain2 when ctl=01 else (others =Z) ; q = datain3 when ctl=10 else (others =Z) ; q = datain0 when ctl=11 else (others =Z) ; end body_tri; 双向端口设计 library ieee; use ieee.std_logic_1164.all; entity bi_state is port (control: in std_logic; input: in std_logic_vector(7 downto 0); IO : inout std_logic_vector(7 downto 0); output: out std_logic_vector(7 downto 0)); end bi_state; architecture one of bi_state is begin process(control,input,IO) begin if (control=0) then output= IO;IO = ZZZZZZZZ; else IO=input;output=ZZZZZZZZ; end if; end process; end one; 分频器设计 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clk_div1 is port(clk_in:in std_logic; clk_out:out std_logic); end clk_div1; architecture one of clk_div1 is begin process(clk_in) variable countQ:std_logi