PWM信号发生器的设计.docVIP

PWM信号发生器的设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BXFSQ IS PORT ( CLK,CLK1,KK : IN STD_LOGIC; DATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); DD : OUT INTEGER RANGE 255 DOWNTO 0 ); END; ARCHITECTURE DACC OF BXFSQ IS SIGNAL Q : INTEGER RANGE 63 DOWNTO 0 ; SIGNAL D : INTEGER RANGE 255 DOWNTO 0 ; SIGNAL FSS : STD_LOGIC ; SIGNAL COUNT12,DATA2,DATA1 : STD_LOGIC_VECTOR(11 DOWNTO 0) ; BEGIN PROCESS(FSS) BEGIN IF (FSSEVENT AND FSS = 1) THEN Q = Q + 1; END IF; E