八位串行输入串行输出冒泡排序verilog.docVIP

实现功能：八位串行输入串行输出冒泡排序 源文件： module bubble_sort(clk,rst,Load,Sort,Send,Data_in,Data_out); input clk,rst,Load,Sort,Send; input [7:0]Data_in; output reg[7:0] Data_out; reg[7:0] A[1:8]; reg[3:0]k; reg[3:0]i,j; reg [2:0]state,nstate; parameter S_rst=3d0; parameter S_init=3d1; parameter S_idle=3d2; parameter S_load=3d3; parameter S_prep=3d4; parameter S_sort=3d5; parameter S_wait=3d6; parameter S_send=3d7; always@(posedge clk or posedge rst) begin if(rst) state=S_rst; else state=nstate; end //状态切换 always@(state or Load or Sort or Send or i or k) begin case(state) S_rst: begin nstate=S_init; end S_init: nstate=S_idle; S_idle: begin if(Load==1b1) nstate=S_load; else if(Sort==1b1) nstate=S_prep; else nstate = S_idle; end S_load: begin if(k==4d8) nstate=S_init; else nstate=S_load; end S_prep: nstate=S_sort; S_sort: begin if(i=j) nstate=S_sort; else if(i=4d8) nstate=S_sort; else if(Send==1b1) nstate=S_send; else nstate=S_wait; end S_wait: begin if(Send==1b1) nstate=Send; else nstate=S_wait; end S_send: begin if(k==4d8) nstate=S_init; else nstate=S_send; end default: nstate=S_rst; endcase end //数据传送 always@(posedge clk) begin case(state) S_rst: ; S_init: begin k=4d0; end S_idle: begin if((Load==1b0)(Sort==1b1)) begin j=4d8; i=4d2; end end S_load: begin if(k4d8) begin k=k+1b1; A[1]=Data_in; A[2]=A[1]; A[3]=A[2]; A[4]=A[3]; A[5]=A[4]; A[6]=A[5]; A[7]=A[6]; A[8]=A[7]; end end S_prep: begin if(A[j-1]A[j]) begin A[j]=A[j-1]; A[j-1]=A[j]; j=j-1b1; end end S_sort: begin if(i=j) if(A[j-1]A[j]) begin A[j]=A[j-1]; A[j-