Quartus_II设计正弦信号发生器.pdf

Quartus II VHDLVerilog VHDLVerilog QuartusII MATLAB DSP Builder FPGA DSP DSP EDA SOPC Builder SOPC QuartusII 4 256M 3.1 VHDL 3.1.1 QuartusII DSP Builder3 3-1 ROMD/A3 ROM 3-1SINGT.VHDFPGA 2 ROM5 ROMROMLPM_ROM LPM_ROMFPGAEABESBCLKf0 64 D/Af f = f0 /64 Project EDA Work Library QuartusII 1,e : \SIN_GNT 2QuartusIIFile→NewNew Device Design Files VHDL Files3-2 VHDL 3-3 VHDL 3-1 3-2 3-3 SINGT.VHD 1 3-4 New Preject Wizard 3-5 3File→Save Ase : \SIN_GNT singt.vhdDo you want to create… : 3.1.2 New Preject Wizardsingt.vhd 1File→New Preject Wizard3-4 …e : \SIN_GNT singt.vhd 3-4 2Next File VHDL()3-5 1 Add AllVHD2 … VHDL 33-5 Next NONEQuartusII NONE 4NextFamilyCyclone YesNextEPIC6Q240C8 3-6 Next 5Finish3-7 3-6 3-7 SINGT 3-8 3.1.3 1Assignmemtssettings Compiler SettingsDeviceEPIC6Q240C8 3-8Available devicesPackagePQFP Pin count240 Speed8 23-8 Device Pin OptionsConfiguration ConfigurationActive Serial PCFPGAJTAGConfiguration deviceEPCS1 EPCS4 EPCS3-9 2 33-9 Programming FilesHexadecimalIntel-Formatoutput File 2 16 fraqtest.hexoutEPROM FPGA 3-9 3-10 .hexout 3.1.4 QuartusII FPGA/CPLD ProcessingStart CompilationCompilation QuartusII Processing Processingvhdl Processing Error:Node instance u1 instabtiates undefined entity DATAROM 3-3DATAROMDATAROM.VHD 3.2 ROM ROM ROM ROM 3.2.1