A Design Assembly Framework for FPGA BackEnd AccelerationFPGA的设计组装框架后端加速度.pdf

A Design Assembly Framework for FPGA Back-End Acceleration Tannous Frangieh and Peter Athanas NSF Center for High-Performance Recongurable Computing (CHREC) Virginia Tech Configurable Computing Lab Department of Electrical and Computer Engineering Blacksburg, Virginia (USA) Email: tannous,athanas@ Abstract—Long wait times constitute a bottleneck limiting the problem. Table I highlights back-end compilation times for number of compilation runs performed in a day, thus risking some FPGA designs. to restrict FPGA adaptation in modern computing platforms. Irrespective of the long run-times, vendor tools excel in the This work presents an FPGA development paradigm as a means to increase FPGA productivity. The practical tasks of logic fidelity of their results, while maximizing device utilization partitioning, placement and routing are examined and a resulting and clock speed. In the process of optimizing designs, the assembly framework, qFlow, is implemented. Experiments show tools flatten carefully crafted hierarchical designs, and re- up to 7x speed-ups using the proposed paradigm compared to implement verified and implemented logic for every design the vendor tool flows. iteration, incurring longer compilation times. For many FPGA Keywords-FPGA; Modular-Assembly; Back-End Acceleration; designers, vendor tools serve the purpose of generating highly Productivity opti