EDA技术实用教程课后答案潘松,黄继业.docVIP

3-3 给出一个4选1多路选择器的VHDL描述。选通控制端有四个输入：S0、S1、S2、S3。当且仅当S0=0时:Y=A；S1=0时:Y=B；S2=0时:Y=C；S3=0时:Y=D。 --解：4选1多路选择器VHDL程序设计。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41a IS PORT( A,B,C,D : IN STD_LOGIC; S0,S1,S2,S3 : IN STD_LOGIC; Y : OUT STD_LOGIC); END ENTITY mux41a; ARCHITECTURE one OF mux41a IS SIGNAL S0_3 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN S0_3=S0S1S2S3; y=A WHEN S0_3=0111 ELSE B WHEN S0_3=1011 ELSE C WHEN S0_3=1101 ELSE D WHEN S0_3=1110 ELSE Z; END ARCHITECTURE one; 3-4 给出1位全减器的VHDL描述；最终实现8位全减器。要求: 1)首先设计1位半减器,然后用例化语句将它们连接起来,图4-20中h_suber是半减器,diff是输出差(diff=x-y),s_out是借位输出(s_out=1,xy),sub_in是借位输入。 图3-19 1位全加器 --解(1.1)：实现1位半减器h_suber(diff=x-y；s_out=1,xy) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_suber IS PORT( x,y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END ENTITY h_suber; ARCHITECTURE hs1 OF h_suber IS BEGIN Diff = x XOR (NOT y); s_out = (NOT x) AND y; END ARCHITECTURE hs1; --解(1.2)：采用例化实现图4-20的1位全减器 LIBRARY IEEE; --1位二进制全减器顺层设计描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_suber IS PORT(xin,yin,sub_in: IN STD_LOGIC; sub_out,diff_out: OUT STD_LOGIC); END ENTITY f_suber; ARCHITECTURE fs1 OF f_suber IS COMPONENT h_suber --调用半减器声明语句 PORT(x, y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END COMPONENT; SIGNAL a,b,c: STD_LOGIC; --定义1个信号作为内部的连接线。 BEGIN u1: h_suber PORT MAP(x=xin,y=yin, diff=a, s_out=b); u2: h_suber PORT MAP(x=a, y=sub_in, diff=diff_out,s_out=c); sub_out = c OR b; END ARCHITECTURE fs1; (2)以1位全减器为基本硬件,构成串行借位的8位减法器,要求用例化语句来完成此项设计(减法运算是x-y-sun_in=difft)。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY suber_8 IS PORT(x0,x1,x2,x3,x4,x5,x6,x7: IN STD_LOGIC; y0,y1,y2,y3,y4,y5,y6,y7,sin: IN STD_