eda课上练习题.pptVIP

习题课 4.4 generic decoder library ieee; use ieee.std_logic_1164.all; entity g44 is generic(n:integer:=3); port(ena: in std_logic; x: out std_logic_vector(2**n-1 downto 0); sel:in integer ); end g44; architecture g of g44 is begin process(ena,sel) variable t1:std_logic_vector(xhigh downto 0); begin t1:=(others=1); if(ena=1) then t1(sel):=0; end if; x=t1; end process; end g; 5.2 priority encoder (a) Using only operators Entity priority_encoder is port(x:in bit_vector(7 downto 1); y:out bit_vector(2 downto 0)); End priority_encoder; Architecture encoder of priority_encoder Begin y(2)=x(7) or x(6) or x(5) or x(4); y(1)=x(7) or x(6) or (( not x(5) and not x(4)) and (x(3) orx(2))); y(0)= x(7) or (not x(6) and (x(5) or (not x(4) and (x(3) or (not x(2) and x(1)))))); End encoder; (b) Using WHEN/ELSE (simple WHEN); library ieee; use ieee.std_logic_1164.all; entity endor is port(x:in std_logic_vector(7 downto 1); y: out std_logic_vector(2 downto 0)); end endor; architecture e of endor is begin y= “111 when x(7)=‘1’ else “110 when x(6)=‘1’ else 101 when x(5)=‘1’ else 100 when x(4)=‘1’ else “011 when x(3)=‘1’ else “010 when x(2)=‘1’ else “001 when x(1)=‘1’ else 000 ; end e; Problem 5.4: Adder Problem 5.4: Adder Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Entity adder is port(a,b:in unsigned(7 downto 0); cin:in std_logic; sel:in std_logic_vector(1 downto 0); sum:out std_logic_vector(7 downto 0); cout: out std_logic); End adder; architecture cp of adder is Signal la,lb,ls:std_logic_vector(8 downto 0); Begin la= ‘0’ a; lb=‘0’ b; ls=la+lb+cin; sum=ls(7 downto 0); cout=ls(8); End cp; Problem 5.5: Signed/Unsigned Adder/Subtractor Problem 5.5: Signed/Unsigned Adder/S