A BiasDependent Model for the Impact of Process.pdfVIP

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error Immunity Hassan Mostafa, M. Anis, and M. Elmasry Abstract— Nanometer SRAM cells are more susceptible to the particle strike soft errors and the increased statistical process variations, in ad- vanced nanometer CMOS technologies. In this paper, an analytical model for the critical charge variations accounting for both die-to-die (D2D) and within-die (WID) variations, over a wide range of bias conditions, is pro- posed. The derived model is verified and compared to Monte Carlo simula- tions by using industrial hardware-calibrated 65-nm CMOS technology. Fig. 1. SRAM cell with the particle strike current pulse . This paper shows the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability. It demonstrates that the adoption of the coupling capacitor reduces the crit- However, all these models consider only the super-threshold SRAM ical charge variability. The derived analytical model accounts for the im- pact of the supply voltage, from 0.1 to 1.2 V, on the critical charge and its cells with only D2D variations taken into account. variability. The tradeoff between performance and power consumption makes Index Terms—Deep sub-micrometer, process variations, reliability, soft the super-threshold SRAM design e