04_STM8S Flash Control System.pptVIP

May 2008 Salim Kandil CONFIDENTIAL STM8SFlash Control System STM8S Technical Training Purpose The purpose of this part is : To present you all the parts of the control system including : Program and Data memory Clock Controller Auto Wake-up and Beeper Supply, Reset, Power Management and Low power Watchdogs To focus on the new functionalities comparing to ST7 Objective At the end of this chapter you will be able to Describes the operations needed to program the memories List all the new features allowing to control the microcontroller Configure the system according to your needs STM8S Memory main features 1/2 Up to 128Kbyte Program memory flash based on EEPROM technology Up to 2K Data EEPROM memory Read While Write capability Write protection with Memory Access Security System MASS keys Programmable write protected User Boot Code area UBC Read Out Protection ROP STM8S Memory main features 2/2 Byte, word and block programming capability 6ms programming time 3ms erase + 3ms write In Circuit Programming ICP and In Application Programming IAP capability One Interrupt vector dedicated to end of programming and attempt to write in protected area Configurable memory state in low power modes Halt and Active Halt Boot ROM embedding ST proprietary boot loader code STM8S Family memory mapping The program memory always starts at address 00 8000h End is determined by the memory size 02 7FFFh for 128K . Interrupt vectors are located at the beginning of this memory area. Programmable User Boot Code area includes the It vectors from 1K up to 128K . The RAM starts from 00 0000h Up to 1KBytes Stack is located at the end of the RAM. The option bytes are located at address 00 4800h after the Data EEPROM which starts from 00 4000h. Memory organization granularities EEPROM access time allows to run the device up to 16 MHz at least without adding wait state. For higher frequency i.e. HSE@24Mhz , one wait state is necessary. Note that there is also the