Lecture12-PLL11-Coupling.pdf

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Lecture12-PLL11-Coupling.pdf

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Spring Semester, 2012 PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 11) Woogeun Rhee Institute of Microelectronics Tsinghua University III. PLL Design 3. Practical Design A. Noise Coupling 2 W. Rhee, Institute of Microelectronics, Tsinghua University Coupling Effect on Clock Jitter JSSC’96, von Kaenel et al. Without Supply Noise SiRF’06, Jenkins et al. With Supply Noise 3 W. Rhee, Institute of Microelectronics, Tsinghua University Review: Effect of External Noise Coupling Ideal Oscillator With Good Isolation With Coupling • Coupling within f /(2Q) will be increased by f /(2Qf ) o o m - Just behaviors like circuit noise!! • Interference coupling near Fout can be reduced only by isolation. 4 W. Rhee, Institute of Microelectronics, Tsinghua University Coupling Mechanism • Substrate noise • Supply noise • Ground bouncing • Crosstalk 5 W. Rhee, Institute of Microelectronics, Tsinghua University Substrate Noise in SoC “Substrate noise coupling is still one of the least understood phenomena in mixed signal/RF